1. Field of the Invention
The present invention relates to a semiconductor storage device, and in particular, to a semiconductor storage device with a structure where memory cell arrays are laminated on the semiconductor substrate.
2. Description of the Related Art
In recent years, an attention is paid to resistance change memories as subsequent candidates of flash memories. The resistive memory devices include narrowly-defined Resistive RAM (ReRAM) and Phase Change RAM (PCRAM). The Resistive RAM store resistance states in a nonvolatile manner with transition metal oxide being used as a recording layer. The Phase Change RAM use chalcogenide as a recording layer and utilize resistance information of crystalline state (conductor) and amorphous state (insulator).
Variable resistance elements of the resistive memories have two kinds of operating modes. One of them is called a bipolar type such that polarity of an applied voltage is switched and thus a high resistant state and a low resistant state are set. The other one is called as a unipolar type such that a voltage value and voltage applying time are controlled without switching the polarity of an applied voltage, and thus the high resistant state and the low resistant state can be set.
In order to realize high-density memory cell arrays, the unipolar type is preferable. This is because that the unipolar type solution enables, without transistors, cell arrays to be configured by superposing variable resistance elements and rectifier elements, such as diodes, on respective intersections between bit lines and word lines. Moreover, large capacity may be achieved without an increase in cell array area by arranging such memory cell arrays laminated in a three-dimensional manner (see, Japanese Unexamined Patent Publication No. (Kohyo) 2005-522045).
Generally in the semiconductor storage devices, a bit line of a memory cell array is connected to a column control circuit including a column decoder and a sense amplifier. A word line of the memory cell array is connected to a row control circuit including a row decoder and a word line driver. In semiconductor storage devices having cross-point type memory cell arrays, the bit line and the word line connected to a selected memory cell are controlled by the column control circuit and the row control circuit, so that an operation for writing/reading data into/from the selected memory cell is performed. Japanese Patent Application Laid-Open No. 2008-077697 describes a control circuit which selectively drives wirings connected to memory cell arrays in a semiconductor storage device. This control circuit is constituted so that two transistors are connected in series, wiring is selected based on a decoder signal, and a high voltage is applied to the selected wiring and a low voltage is applied to nonselected wirings.
In resistive memory devices having a memory block where memory cell arrays are laminated, in order to reduce an entire chip size, a control circuit is occasionally arranged on a semiconductor substrate below the memory block. In order to arrange the control circuit within an area below the memory block, a circuit area of the control circuit should be reduced. For this reason, it is required to simplify the configuration of the control circuit for selectively driving the wirings connected to the memory cell arrays.